1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device and method for manufacturing a semiconductor device which, on performing a “via first” Dual Damascene process, inhibits or prevents the formation of a void in a bottom anti-reflective coating filling a via hole.
2. Description of the Background
Generally, with the high integration of semiconductor devices, an interconnect becomes narrowed. The narrowing of the interconnect generally causes an increase of resistance in the interconnect and furthermore a delay of signal transfer. To solve the problem of signal transfer delay, a multi-layered interconnect structure has been introduced, generally replacing the previous single layered interconnect structure.
However, in the multi-layered interconnect structure, an interval (or spacing) between adjacent interconnect lines is further narrowed so that parasitic capacitance between interconnects on the same layer increases and signal transfer delay of the semiconductor device further increases. Particularly, in case of an interconnect with relatively fine line width, signal transfer delay due to parasitic capacitance between interconnects has a marked effect on operational properties of semiconductor devices. To reduce parasitic capacitance between interconnects, it is preferable to reduce the thickness of interconnect and to thicken an interlayer dielectric. Accordingly, many proposals have been provided, wherein the interconnect is formed of low specific resistance material (for example, copper), and the interlayer dielectric includes one or more low permittivity materials. However, in case of copper, since vapor pressure of certain etching by-products is low, it is generally difficult to dry etch copper.
To solve this problem, a Damascene process has been recently proposed. In one Damascene process, a via hole or contact hole is formed in the interlayer dielectric, copper is deposited to fill the via hole or contact hole, and then excess copper is removed by means of planarization, thus forming a copper interconnect.
Meanwhile, Dual Damascene processes are generally classified into at least three types: a “via first” method, a “trench first” method, and a “self-aligned” method. In the via first method, an interlayer dielectric is etched to form a via hole, and the interlayer dielectric is then etched to form a trench over the via hole. On the contrary, in the trench first method, a trench is first formed, and a via hole is then formed under the trench. In the self-aligned method, a via hole hard mask (typically formed using an etch stop layer) is aligned with a trench mask, and both the via hole and the trench are then formed with one etch step. Among the above methods, the via first method has been widely used.
A conventional “via first” Dual Damascene process is now explained with reference to FIGS. 1A to 1D. First, as shown in FIG. 1A, a first interlayer dielectric 102 with low permittivity (for example, a borophosphosilicate glass [BPSG] layer) is deposited on a semiconductor substrate 101 on which a device such as a transistor (not shown) has been formed. Then, an etch stop layer 103 (e.g., formed of silicon nitride) is deposited on the first interlayer dielectric 102, and a second interlayer dielectric 104 with low permittivity (for example, a SiH4-based silicon oxide layer) is then deposited on the etch stop layer 103. Then, a photoresist is applied on the second dielectric 104, and the photoresist is then patterned to form a first photoresist pattern 105 exposing a portion of the second interlayer dielectric 104 corresponding to a via hole region.
In this state, as shown in FIG. 1B, using the first photoresist pattern 105 as an etching mask, the exposed second interlayer dielectric 104 is etched and removed to expose the etch stop layer 103. The etching process is continuously performed so that the exposed etch stop layer 103 and the first interlayer dielectric 102 are sequentially etched and removed to form a via hole 106.
Then, as shown in FIG. 1C, a BARC 107 (Bottom Anti-Reflective Coating) is coated to a desired thickness on the resultant structure, filling the via hole 106. Herein, a conventional BARC 107 is composed of an acrylate based polymer (having pendant anthracene based chromophore and hydroxide groups), a cross-linking agent, a surfactant, a thermal acid generator (TAG) and solvent (PGMEA, PGME, EL, NBA and so on), etc. Then, a photoresist is applied on the resultant structure including BARC 107, and the photoresist is patterned to form a second photoresist pattern 108 exposing a portion of BARC 107 corresponding to a trench region.
Then, as shown in FIG. 1D, using the second photoresist pattern 108 as an etching mask, the exposed BARC 107 and second interlayer dielectric 104 are etched and removed to form a trench 109. Then, as shown in FIG. 1E, the second photoresist pattern 108 and the remaining BARC 107 are removed. Thereafter, a metal layer (not shown) fills the via hole 106 and the trench 109. The metal layer is then planarized by chemical mechanical polishing, thus completing the conventional via first Dual Damascene process.
Also, an alternative conventional via-first Dual Damascene process known as the Photoresist recess (PR recess) method may be used. According to the PR recess Dual Damascene method, a via hole is formed in interlayer dielectrics on a substrate, and the via hole is then sufficiently filled with a novolac resin. Thereafter, the novolac resin is recessed by an ashing process using an O2 plasma. Then, a back side wet etch is performed on the resultant structure. Therefore, only a portion of via hole is filled with the novolac resin. Then, a conventional BARC comprising an acrylate based resin is coated on the resultant structure, sufficiently filling the remaining portion of the via hole, and a photoresist is applied on the BARC and patterned to form a photoresist pattern for a subsequent trench. And, using the photoresist pattern, the interlayer dielectrics are selectively etched to form the trench.
As described above, according to the conventional via first Dual Damascene process, the via hole is first formed, and then the BARC fills in the via hole in order to form the trench. However, with the high integration of semiconductor devices, an interconnect may be sufficiently narrowed so that the critical dimension (CD) of the via hole for the interconnect is also reduced. Thus, the BARC may fill the via hole sufficiently incompletely to produce a void (indicated as 107a in FIG. 1C).
Due to the void 107a formed in the BARC filling the via hole, in the subsequent trench formation process using the second photoresist pattern, a fence (indicated as 103a in FIG. 1D) may be formed, or a bottom face of the trench may not be uniformly etched, thereby deteriorating process reliability.
Also, according to the above-mentioned PR recess Dual Damascene method, since ashing of novolac resin and back side wet etching should be performed, the overall process is relatively complex and the process time becomes relatively long. Also, in the PR recess Dual Damascene method, additional etching equipment may be necessary.